The present invention is generally directed to built-in self-test logic circuitry used in conjunction with the design of electronic integrated circuit chip devices and systems. More particularly, the present invention is directed to circuits and a method for testing logic blocks which include memory arrays embedded therein.
As the packing density of integrated circuit chip devices has become greater, there has also appeared a greater need for the testing of such devices. In particular, built-in self-test methodologies have provided decided advantages in a wide range of circumstances. Even more particularly, the self-test method which employs level sensitive scan design (LSSD) methodology has proven to be particularly effective. In this approach to self-test, shift register latches, usually comprising a master and slave latch in each shift register latch pair, are connected together in a long scan string which operates in many ways like a shift register. These scan strings are provided with data which is used to drive blocks of combinatorial logic which are being tested. Likewise, scan strings are also employed to collect output signals from these logic blocks in response to known, albeit pseudo-random, input signals. These logic blocks are typically constructed using computer aided design methodology which models ideal physical behaviors. However, during fabrication it is possible to produce circuits which do not perform in complete conformance with the model. However, the computer aided design methods do provide a method of being able to define desired output sequences given specified input sequences. Thus it is generally possible to determine if the output signals collected via the scan strings represent desired output responses.
Because of the increasing complexity of these circuits and the number of possible input and internal state conditions, it is not possible to do exhaustive tests because the number of test vectors that would have to be employed is too large for test operations to be run in a reasonable length of time. Accordingly, pseudo-random pattern testing is employed. In this methodology, pseudo-random patterns are generated as input data to the logic block being tested. This pseudo-random data is typically generated by means of a pseudo-random pattern generator which is typically provided in the form of a linear feedback shift register (LFSR) whose outputs are used to provide pseudo-random data to one or more scan strings of shift register latches. The linear feedback shift register is typically constructed so as to cycle through pseudo-random state conditions in a manner in which a maximum amount of time elapses before a state is repeated. This is accomplished through suitable and well known methods for connecting the feedback elements in the LFSR.
The above methodology is very effective for testing blocks of logic circuitry. However, in those situations in which the block of logic circuitry includes an array structure, testing becomes much more difficult. Such array structures provide a memory function within the logic block. More particularly, the memory function provided by an array is such that, for test purposes, it is extremely desirable to be able to test or exercise each cell in the array. For purposes of the present discussion, the term "cell" is used to refer to all of those memory bit positions which are accessable using a single address. In order to test every cell in the array, it is necessary to access the array using all possible addresses. However, there is a significant problem in doing this using pseudo-random test data which is scanned into shift register latch scan strings. This pseudo-random data cannot guarantee the generation of all of the addresses needed to initialize cells in the embedded array and likewise cannot guarantee access to all of the data contained in the array for the same reason.
Moreover, for the initialization of embedded arrays for test purposes, one needs to know what values are stored in the array. It is noted however that it does not matter what values are stored, but only that their values can be ascertained ahead of time and can be repeated. However, since it is possible to externally control starting states of LFSR devices and to therefore provide known scan-in data to the scan strings, it is always possible to supply data input to various cell location in the array. Even though this data is effectively pseudo-random, it is still nonetheless known. However, with respect to the addresses, pseudo-random data supplied to the address lines of the array is not by itself sufficient to insure complete coverage of every address in the array. Thus, built-in self-test methodologies employing pseudo-random pattern excitation for array initialization purposes is difficult to apply when there is an array embedded within the block of logic being tested. Furthermore, there is an additional constraint in that when the tests are over, one wishes to ascertain what is finally in the array.
Additionally, it is noted that when logic blocks contain arrays, self-test isolation effectiveness would be greatly increased if there was a capability to rapidly initialize arrays with pseudo-random patterns and to rapidly form signatures on the array contents. These signatures are typically generated from scan out data which is used to drive a sensitive linear feedback shift register whose end state is very much dependent upon correct input of signals shifted out of the scan string.
Additionally, it is noted that in any given block of logic which is part of the built-in self-test LSSD methodology, it is also possible to encounter circumstances in which the block contains multiple numbers of array structures. Thus the problem of testing arrays becomes that much more difficult.
It is also noted that in logic testing in general, isolation effectiveness for error conditions is important. Thus, it is generally desirable to be able to break up a test into a series of many short tests each consisting of a much smaller number of patterns without loss of test coverage. In order to achieve this objective, it is important that arrays which are present in logic blocks be initialized quickly not only because the pseudo-random initialization state of arrays results in pseudo-random data from the array almost immediately, even for the first few patterns of a test but also because array contents are quickly checked. Thus, in any test mechanism, there should be a mechanism for the ability to perform multiple short tests as opposed to one long test because of the superior isolation results for failing test conditions. Thus with short tests, quicker isolation of faults during manufacturing and in the field is possible.